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NCP5680
PIN DESCRIPTIONS
Pin
1
2
Name
VSD
PHSEN
Type
OUTPUT,
POWER
INPUT,
ANALOG
Description
This pin provides the 2.5 V Photo sense bias voltage. The bias voltage is connected when either
a flash sequence has been selected, or the ENPH bit, in the CONFIG0 register, is set High. The
output current is limited to 1 mA. The same pin is used to synchronize the charge pump operation
by an external digital signal (see Figure 6).
This pin fulfills two functions:
PHOTO SENSE FUNCTION: the pin is connected to the external photo transistor. The operating
voltage is limited in the 0 V to 1.7 V range. The voltage signal developed across that pin and
ground during a flash sequence is compared with the PHREF voltage (encoded in one I2C data
byte) to stop the flash pulse when the illumination is completed. This function is activated by the
ENPH bit of the CONFIG0 register:
ENPH = 0 3 the Photo sense is not activated, the flash time depends solely upon the TRIGFL
pulse width, but is automatically limited by the Time out.
ENPH = 1 3 the Photo sense is activated, the flash time depends upon the TRIGFL duration
and the amount of light reflected by the scene, but limited by the Time Out.
The PHREF reference is setup by the external MCU and stored into a built ? in register through
the I2C lines.
CHARGE PUMP SYNC: the charge pump is de ? activated when an external DC voltage (V MSK ),
in the 2.1 V to 2.5 V range, is applied to the PHSEN pin, whatever be the status of the photo
sense transistor. The PHSEN resumes to the normal operation when the V MSK voltage is discon-
nected from the pin.
3
4
5
SCL
SDA
TRIGFL
INPUT,
DIGITAL
INPUT,
DIGITAL
INPUT,
DIGITAL
This pin carries the I2C clock to control the DC/DC converter and to set up the output current.
The SCL clock is associated with the SDA signal.
This pin carries the data provided by the I2C protocol. A normal I2C sequence must send the I2C
address plus a pair of SDA byte to properly program the embedded registers.
This pin supports the digital signal coming from an external peripheral to trig the flash pulse. The
duration of this positive pulse drives the LED, the photo sense being a way to accurately control
the illumination of the scene. The TRIGFL signal is independent from the I2C interface, assuming
the supercap has been properly charged to the appropriate voltage prior to launch the flash trig-
ger. The built ? in time out makes sure the flash duration does not extend the programmed limit
(ranging from 2 ms to 200 ms).
In addition, an internal pull ? down resistor (100 k W typical) makes sure the pin is not floating when
it is not connected to an external network.
6
7
8
9
NTC
Is2
Vgs2
Vds2
INPUT,
ANALOG
INPUT,
ANALOG
OUTPUT,
POWER
INPUT,
ANALOG
This pin monitors the external Negative Temperature Coefficient resistor. A programmable con-
stant current is provided by the pin (10 m A typical) and the internal structure compares the result-
ing voltage against the programmed limit, the result being a stop of the power current when V NTC
is lower than Vlimit.
This pin, associated to Vgs2 and the Vout pin, returns the sense voltage, developed across the
external shunt resistor, to the LED#2 current control loop. Care must be observed to avoid noise,
stray capacitance and parasitic ohmic element between the shunt resistor and this point to min-
imize the parasitic pulses on the LED output current.
This pin controls the gate of the external NMOS device and the LED is activated when the bit
BLED1=1 in the Select Register byte. Care must be observed to minimize the routing between
this pin and the gate of the external device. Similarly, the PCB track shall be designed to sustain
the relative high current pulse flowing into the Ciss during the normal operation. The built ? in
driver structure is capable to control 10 A rated NMOS device with Ciss up to 2500 pF.
This pin fulfils two functions:
? support the I ? LED when the Torch mode is activated. In this case, the Gate drive Vgs1 and
Vgs2 signals are deactivated. The internal current mirror, programmed by the I2C port, limits the
ILED1 to 100 mA maximum.
? sense the Drain voltage across the external NMOS #2 to detect the overload condition: see
Table 2.
1. Using low ESR ceramic capacitor, X5R type, is mandatory to optimize the Charge Pump efficiency and to reduce the EMI. Care must be
observed to prevent large influence of the ceramic capacitor DC bias: using 10 V rated capacitor, 0805 or 0603 size, is recommended.
2. Total DC/DC output current is limited to 500 mA
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